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Oscillator circuits and methods for realignment of an oscillator circuit

專(zhuān)利號(hào)
US10868496B1
公開(kāi)日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company Limited（TW Hsinchu）
發(fā)明人
Tsung-Hsien Tsai; Ruey-Bin Sheen; Chih-Hsien Chang; Cheng-Hsiang Hsieh
IPC分類(lèi)
H03B5/12; H03B5/04; H03L7/081; H03K3/00; H03B17/00; H03L7/26; H03K5/156
技術(shù)領(lǐng)域
rlb,oscillator,rl,signal,terminal,pmos,in,nmos,transistor,first
地域： Hsinchu

摘要

Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

說(shuō)明書(shū)

BACKGROUND

Generally, an integrated circuit (“IC”) is a circuit in which all or some of the circuit elements are inseparably associated and electrically interconnected so that it is considered to be indivisible. An IC is commonly embodied in a wafer. A wafer can be a slice or flat disk of semiconductor material or, for example, of semiconductor material deposited on a substrate, in which circuits or devices are simultaneously processed and, if there is more than one device, subsequently separated into dies. The wafer can have logic circuitry that forms a high-speed digital circuit, such as digital logic for a digital phase locked loop (“PLL”) circuit, for example.

The digital PLL circuit may utilize an inductance-capacitance (LC) oscillator or another type of oscillator. An LC oscillator includes a parallel electrical connection between a capacitor element and an inductor element. This parallel connection results in an electrical resonator that stores energy oscillating at the circuit's resonant frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of an oscillator, in accordance with some embodiments.

FIGS. 2A and 2B depict example realignment circuits, in accordance with some embodiments.

權(quán)利要求

1
What is claimed is:1. An oscillator comprising:an inductor having first and second terminals;a capacitor electrically coupled in parallel to the inductor at the first and second terminals; anda first transistor of a first conductivity type that (i) is electrically coupled to the first terminal and a voltage source, and (ii) includes a gate configured to receive a first realignment signal, the first transistor being turned on and a voltage of the first terminal being increased from a low level to a high level in order to align a phase of a waveform of the oscillator when the first realignment signal is in a realignment state.2. The oscillator of claim 1, wherein a drain of the first transistor is electrically coupled to the first terminal, and a source of the first transistor is electrically coupled to the voltage source.3. The oscillator of claim 1, wherein when the first realignment signal is in the realignment state, the voltage of the first terminal is increased to a voltage level of the voltage source.4. The oscillator of claim 1, whereinwhen the first realignment signal is in a normal state, the first transistor is turned off, anda voltage level of the first realignment signal in the normal state is opposite to the voltage level of the first realignment signal in the realignment state.5. The oscillator of claim 1 further comprising:a second transistor of a second conductivity type that (i) is electrically coupled to the second terminal and ground, and (ii) includes a gate that is configured to receive a second realignment signal, wherein when the second realignment signal is in a realignment state, the second transistor is turned on and a voltage of the second terminal is decreased from a high level to a low level in order to align the phase of the waveform of the oscillator.6. The oscillator of claim 5, wherein a drain of the second transistor is electrically coupled to the second terminal, and a source of the second transistor is electrically coupled to the ground.7. The oscillator of claim 5, wherein when the second realignment signal is in the realignment state, the voltage of the second terminal is decreased to a voltage level of the ground.8. The oscillator of claim 5, whereinwhen the second realignment signal is in a normal state, the second transistor is turned off, anda voltage level of the second realignment signal in the normal state is opposite to the voltage level of the second realignment signal in the realignment state.9. The oscillator of claim 5, wherein the first conductivity type is P-type, the second conductivity type is N-type.10. The oscillator of claim 5 further comprising:a pulse generator configured to (i) receive a clock signal, and (ii) generate the first realignment signal and the second realignment signal as differential signals based on the clock signal.11. An oscillator comprising:an inductor having first and second terminals;a capacitor electrically coupled in parallel to the inductor at the first and second terminals;a plurality of first transistors of a first conductivity type, each of the first transistors (i) being electrically coupled to the first terminal and a voltage source, and (ii) having a gate that is configured to receive a first realignment signal, the voltage of the first terminal being increased from a low level to a high level in order to align a phase of a waveform of the oscillator when the first realignment signal is in a realignment state; anda first circuit configured to gate the first realignment signal based on a first control signal to selectively provide the first realignment signal to the gates of the plurality of first transistors.12. The oscillator of claim 11, wherein the first circuit comprises an array of OR gates.13. The oscillator of claim 11, wherein the first control signal enables the first realignment signal to be provided to selected gates of the plurality of first transistors while not providing the first realignment signal to non-selected gates of the plurality of first transistors.14. The oscillator of claim 11 further comprising:a plurality of second transistors of a second conductivity type, each of the second transistors (i) being electrically coupled to the second terminal and ground, and (ii) having a gate that is configured to receive a second realignment signal, wherein when the second realignment signal is in a realignment state, a voltage of the second terminal is decreased from a high level to a low level in order to align the phase of the waveform of the oscillator; anda second circuit configured to gate the second realignment signal based on a second control signal to selectively provide the second realignment signal to the gates of the plurality of second transistors.15. The oscillator of claim 14, wherein the first conductivity type is P-type, the second conductivity type is N-type.16. The oscillator of claim 14 further comprising:a pulse generator configured to (i) receive a clock signal, and (ii) generate the first realignment signal and the second realignment signal as differential signals based on the clock signal.17. A method for realigning an oscillator that comprises an inductor having first and second terminals, a capacitor electrically coupled in parallel to the inductor at the first and second terminals, and a first transistor of a first conductivity type coupled to the first terminal, the method comprising:providing a first realignment signal to a gate of the first transistor, the first realignment signal including a realignment state and a normal state, and a voltage level of the first realignment signal in the normal state being opposite to the voltage level of the first realignment signal in the realignment state;when the first realignment signal is in the realignment state, turning on the first transistor and increasing a voltage of the first terminal from a low level to a high level in order to align a phase of a waveform of the oscillator; andturning off the first transistor when the first realignment signal is in the normal state.18. The method of claim 17, wherein the oscillator comprises a second transistor of a second conductivity type coupled to the second terminal, the method further comprising:providing a second realignment signal to a gate of the second transistor, the second realignment signal including a realignment state and a normal state, and a voltage level of the second realignment signal in the normal state being opposite to the voltage level of the second realignment signal in the realignment state; andwhen the second realignment signal is in the realignment state, turning on the second transistor and decreasing a voltage of the second terminal from a high level to a low level in order to align the phase of the waveform of the oscillator.19. The method of claim 18, further comprising turning off the second transistor when the second realignment signal is in the normal state.20. The method of claim 18, wherein the oscillator comprises a pulse generator, the method further comprising:providing a clock signal to the pulse generator; andusing the pulse generator to generate the first realignment signal and the second realignment signal as differential signals based on the clock signal.
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