In this way, the strength of the realignment circuit 402 is controlled by the first strength control word 518 because if there are more logic low bits in the first strength control word 518, then more PMOS transistors 511 are turned on when the first realignment signal RLB is in its realignment state (e.g., logic level low). Turning on a greater number of the PMOS transistors 511 results in a larger impact of the realignment circuit 402 because the additional turned on PMOS transistors 511 supply more current to terminal 116, which causes the voltage of the terminal 116 to be pulled up more quickly towards the voltage of voltage source 515.

An example of the realignment circuit 404 is illustrated in FIG. 5B. In this figure, the realignment circuit 404 includes a plurality of NMOS transistors 521 and an array of logic AND gates 526 for selectively activating the NMOS transistors 521. The example realignment circuit 404 of FIG. 5B includes four NMOS transistors 521 and four corresponding AND gates 526, but other numbers of NMOS transistors and corresponding AND gates are used in other embodiments to provide for a variety of resolutions of realignment strength control.