When the second realignment signal RL is in its realignment state with a high logic level, the realignment circuit 404 provides realignment with the strength of the realignment being determined by the second strength control word 528. Specifically, each AND gate of the AND gates 526 that receives a logic low input from the strength control word 528 outputs a logic low signal, and therefore turns off the corresponding NMOS transistor 521 that receives the logic low signal at its gate. Each AND gate of the AND gates 526 that receives a logic high input from the strength control word 528 outputs a logic high signal when the second realignment signal RL is in its realignment state, and therefore turns on the corresponding NMOS transistor 521 that receives the logic high signal at its gate. The NMOS transistors 521 that are turned on pull down the voltage of the terminal 118 by supplying current from the drain terminal 524 through the source terminal 522 and into the electrical ground 525. The NMOS transistors 521 that are turned off do not pull down the voltage of the terminal 118 and thus do not contribute to the realignment.

In this way, the strength of the realignment circuit 404 is controlled by the second strength control word 528 because if there are more logic high bits in the second strength control word 528, then more NMOS transistors 521 will be turned on when the second realignment signal RL is in its realignment state (e.g., logic level high). Turning on a greater number of the NMOS transistors 521 results in a larger impact of the realignment circuit 404 because the additional turned on NMOS transistors 521 cause the voltage of the terminal 118 to be pulled down more quickly towards the voltage of the electrical ground 525.