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Oscillator circuits and methods for realignment of an oscillator circuit

專利號(hào)
US10868496B1
公開(kāi)日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company Limited（TW Hsinchu）
發(fā)明人
Tsung-Hsien Tsai; Ruey-Bin Sheen; Chih-Hsien Chang; Cheng-Hsiang Hsieh
IPC分類
H03B5/12; H03B5/04; H03L7/081; H03K3/00; H03B17/00; H03L7/26; H03K5/156
技術(shù)領(lǐng)域
rlb,oscillator,rl,signal,terminal,pmos,in,nmos,transistor,first
地域： Hsinchu

摘要

Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

說(shuō)明書(shū)

As seen in the example embodiment of FIG. 6, a first bit of the three-bit width control signal [2:0] is received at the NAND gate 606, a second bit of the three-bit width control signal [2:0] is received at the NAND gate 608, and a third bit of the three-bit width control signal [2:0] is received at the NAND gate 610. The table below illustrates an example scheme by which the three-bit width control signal [2:0] may be used to control the width of the pulses generated by the pulse generator 600:

Width control[2.0] Pulse width 3'b001 Level0 (narrow) 3'b010 Level1 (middle) 3'b100 Level2 (wide)

權(quán)利要求

1
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