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Oscillator circuits and methods for realignment of an oscillator circuit

專利號(hào)
US10868496B1
公開日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company Limited(TW Hsinchu)
發(fā)明人
Tsung-Hsien Tsai; Ruey-Bin Sheen; Chih-Hsien Chang; Cheng-Hsiang Hsieh
IPC分類
H03B5/12; H03B5/04; H03L7/081; H03K3/00; H03B17/00; H03L7/26; H03K5/156
技術(shù)領(lǐng)域
rlb,oscillator,rl,signal,terminal,pmos,in,nmos,transistor,first
地域: Hsinchu

摘要

Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

說明書

According to some embodiments, the S2D unit 624 converts the single-ended output signal to differential signals RL and RLB. The differential signals RL and RLB may be used as complementary realignment signals, as described above with reference to the preceding figures. The S2D unit 624 includes an even-staged inverter train 628, an odd-staged inverter train 626, and a crossing latch unit 630. According to some embodiments, the even-staged inverter train 628 includes an even number (e.g., 2, 4, etc.) of serially connected inverters, and the odd-staged inverter train 610 includes an odd number (e.g., 1, 3) of serially connected inverters. The crossing latch unit 630 includes a pair of cross-connected inverters as shown in FIG. 6. The respective outputs of the inverter trains 626, 628 are received by the crossing latch unit 630, and the outputs of the crossing latch unit 630 are received by a circuit 632 including a NAND gate, NOR gate, and two inverters electrically coupled as shown in the figure.

The circuit 632 further receives a two-bit control signal RL_CON[1:0] and controls the output of the RL and RLB realignment signals based on that control signal. Specifically, the example pulse generator 600 of FIG. 6 uses the two-bit control signal RL_CON[1:0] to control whether (i) the realignment signals RL and RLB are both off, (ii) the realignment signals RL and RLB are both on, or (iii) one of the realignment signals RL, RLB is turned on and the other signal is turned off. In this manner, the pulse generator 600 can output one, both, or neither of the realignment signals RL, RLB to control the realignment strength of the oscillator.

權(quán)利要求

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