CMOS input stage circuits and related methods
地域：
TX
TX Austin
摘要
Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.
說明書
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This disclosure relates to operational amplifiers and, more particularly, to an input stage of an operational amplifier.
The following descriptions and examples are provided as background only and are intended to reveal information that is believed to be of possible relevance to the present invention. No admission is necessarily intended, or should be construed, that any of the following information constitutes prior art impacting the patentable character of the subjected matter claimed herein.
Operational amplifiers are commonly used in electronic circuit design to amplify an input signal and provide an amplified output signal. An operational amplifier typically includes an input stage for the initial amplification and an output stage for providing drive capability and possibly further amplification. In some cases, the amplifier may further include intermediate stages for level shifting and conversion to single-ended operation.
The input stage of an operational amplifier provides the initial gain and usually defines the bandwidth of the amplifier. The input stage has at least one associated transconductance (gm), or gain between the input voltage signal and the current supplied to either the intermediate stages or the final output stage of the amplifier. It is generally desirable for the input stage to have a constant transconductance to provide constant bandwidth and constant gain for the amplifier. If the transconductance of the input stage varies, the amplifier bandwidth will vary which has a direct impact on the amplifier stability.
權利要求
What is claimed is:1. A complementary metal-oxide-semiconductor (CMOS) input stage circuit, comprising:a pair of NMOS input transistors and a first pair of PMOS input transistors, each coupled to receive differential input voltages at gate terminals thereof; a first current source coupled to source terminals of the first pair of PMOS input transistors and configured to generate a first current; a current steering circuit coupled to receive a cross-over voltage and configured to steer the first current to the pair of NMOS input transistors or to the first pair of PMOS input transistors or to both, depending on whether a common-mode input voltage is significantly greater than, significantly less than or substantially equal to the cross-over voltage; and a current stealing circuit coupled to receive the cross-over voltage and configured to steal a portion of the first current, so that a smaller remaining portion of the first current is divided among the pair of NMOS input transistors and the first pair of PMOS input transistors when the common-mode input voltage is substantially equal to the cross-over voltage. 2. The CMOS input stage circuit recited in claim 1 , wherein:the pair of NMOS input transistors have source terminals that are coupled together and drain terminals coupled to a first current summation circuit of the CMOS input stage circuit; and the first pair of PMOS input transistors have source terminals that are connected together and drain terminals coupled to a second current summation circuit of the CMOS input stage circuit. 3. The CMOS input stage circuit recited in claim 1 , wherein the current steering circuit comprises:a first PMOS transistor having a source terminal coupled to the source terminals of the first pair of PMOS input transistors and a gate terminal coupled to receive the cross-over voltage; and a first NMOS current mirror coupled between a drain terminal of the first PMOS transistor and source terminals of the pair of NMOS input transistors. 4. The CMOS input stage circuit recited in claim 3 , wherein:when the common-mode input voltage is significantly greater than the cross-over voltage, the first PMOS transistor turns on and the first current flows through the first PMOS transistor and is mirrored by the first NMOS current mirror to the source terminals of the pair of NMOS input transistors; when the common-mode input voltage is significantly less than the cross-over voltage, the first PMOS transistor turns off and the first current is supplied to the source terminals of the first pair of PMOS input transistors; and when the common-mode input voltage is substantially equal to the cross-over voltage, the first PMOS transistor partially turns on, such that a first portion of the remaining portion of the first current is supplied to the pair of NMOS input transistors and a second portion of the remaining portion of the first current is supplied to the first pair of PMOS input transistors. 5. The CMOS input stage circuit recited in claim 1 , wherein the current stealing circuit comprises:a second PMOS transistor having a source terminal coupled to the source terminals of the first pair of PMOS input transistors and a gate terminal coupled to receive the cross-over voltage; and a second NMOS current mirror coupled between drain terminals of the second pair of PMOS input transistors and a drain terminal of the second PMOS transistor. 6. The CMOS input stage circuit recited in claim 5 , wherein the second NMOS current mirror acts like a current source for generating a stolen current, which is stolen from the first current, when the common-mode input voltage is substantially equal to the cross-over voltage, and wherein the second PMOS transistor acts like a switch to turn the stolen current on/off. 7. The CMOS input stage circuit recited in claim 6 , wherein the stolen current generated by the second NMOS current mirror is substantially equal to about one-quarter to about one-half of the first current. 8. The CMOS input stage circuit recited in claim 6 , wherein:when the common-mode input voltage is greater than or equal to the cross-over voltage, the second PMOS transistor turns on to conduct the stolen current; and when the common-mode input voltage is less than the cross-over voltage, the second PMOS transistor turns off to cut off the stolen current. 9. The CMOS input stage circuit recited in claim 5 , wherein the current stealing circuit further comprises:a second pair of PMOS input transistors having source terminals that are connected together and gate terminals couples to receive the differential input voltages; a second current source coupled to the source terminals of the second pair of PMOS input transistors and configured to generate a second current; a third PMOS transistor having a source terminal coupled to the source terminals of the second pair of PMOS transistors and a gate terminal coupled to receive the cross-over voltage; and a third NMOS transistor having gate and drain terminals coupled to the drain terminal of the third PMOS transistor and a source terminal coupled to ground. 10. The CMOS input stage circuit recited in claim 9 , wherein the third PMOS transistor is configured to prevent or allow the second current to flow through the second pair of PMOS input transistors to the second NMOS current mirror, depending on whether the common-mode input voltage is greater than or less than the cross-over voltage. 11. The CMOS input stage circuit recited in claim 9 , wherein when the common-mode input voltage is significantly greater than the cross-over voltage, the third PMOS transistor turns on to prevent the second current from flowing through the second pair of PMOS input transistors to the second NMOS current mirror, which prevents the second NMOS current mirror from generating the stolen current. 12. The CMOS input stage circuit recited in claim 9 , wherein when the common-mode input voltage is significantly less than the cross-over voltage:the third PMOS transistor turns off to allow the second current to flow through the second pair of PMOS input transistors to the second NMOS current mirror, which enables the second NMOS current mirror to generate the stolen current; and the second PMOS transistor turns off to cut off the stolen current. 13. The CMOS input stage circuit recited in claim 9 , wherein when the common-mode input voltage is substantially equal to the cross-over voltage:the third PMOS transistor partially turns on to allow the second current to flow through the second pair of PMOS input transistors to the second NMOS current mirror, which enables the second NMOS current mirror to generate the stolen current; and the second PMOS transistor partially turns on to conduct the stolen current that is stolen from the first current. 14. A method for a complementary metal-oxide-semiconductor (CMOS) input stage circuit comprising a pair of NMOS input transistors and a first pair of PMOS input transistors, the method comprising:supplying differential input voltages to gate terminals of the pair of NMOS input transistors and the first pair of PMOS input transistors; steering a first current to the pair of NMOS input transistors or to the first pair of PMOS input transistors or to both, depending on whether a common-mode input voltage is significantly greater than, significantly less than or substantially equal to a cross-over voltage; and stealing a portion of the first current, so that a smaller remaining portion of the first current is divided among the pair of NMOS input transistors and the first pair of PMOS input transistors when the common-mode input voltage is substantially equal to the cross-over voltage to maintain near constant transconductance (gm) across the common-mode input voltage range of the CMOS input stage circuit. 15. The method as recited in claim 14 , further comprising maintaining the first current supplied to the pair of NMOS input transistors or the first pair of PMOS input transistors when the common-mode input voltage is significantly greater than or significantly less than the cross-over voltage, respectively. 16. The method as recited in claim 14 , wherein said steering a first current comprises:steering the first current to the pair of NMOS input transistors when the common-mode input voltage is significantly greater than the cross-over voltage; steering the first current to the first pair of PMOS input transistors when the common-mode input voltage is significantly less than the cross-over voltage; and steering a first portion of the smaller remaining portion of the first current to the pair of NMOS input transistors and a second portion of the smaller remaining portion of the first current to the first pair of PMOS input transistors when the common-mode input voltage is substantially equal to the cross-over voltage. 17. The method as recited in claim 14 , wherein the CMOS input stage circuit further comprises:a second pair of PMOS input transistors having source terminals that are connected together and gate terminals coupled to receive the differential input voltage; a second current source coupled to the source terminals of the second pair of PMOS input transistors and configured to generate a second current; a second PMOS transistor having a source terminal coupled to the source terminals of the first pair of PMOS input transistors and a gate terminal coupled to receive the cross-over voltage; a second NMOS current mirror coupled between drain terminals of the second pair of PMOS input transistors and a drain terminal of the second PMOS transistor; and a third PMOS transistor having a source terminal coupled to the source terminals of the second pair of PMOS transistors and a gate terminal coupled to receive the cross-over voltage. 18. The method as recited in claim 17 , wherein the second NMOS current mirror acts like a current source for generating a stolen current, which is stolen from the first current, when the common-mode input voltage is substantially equal to the cross-over voltage, and wherein the second PMOS transistor acts like a switch to turn the stolen current on/off. 19. The method as recited in claim 18 , wherein said stealing a portion of the first current comprises stealing a portion of the first current only when the common-mode input voltage is substantially equal to the cross-over voltage by:partially turning on the third PMOS transistor to allow the second current to flow through the second pair of PMOS input transistors to the second NMOS current mirror, which enables the second NMOS current mirror to generate the stolen current; and partially turning on the second PMOS transistor to conduct the stolen current, which is stolen from the first current. 20. The method as recited in claim 18 , further comprising maintaining the first current supplied to the pair of NMOS input transistors when the common-mode input voltage is significantly greater than the cross-over voltage by:turning on the third PMOS transistor to prevent the second current from flowing through the second pair of PMOS input transistors to the second NMOS current mirror, which prevents the second NMOS current mirror from generating the stolen current. 21. The method as recited in claim 18 , further comprising maintaining the first current supplied to the first pair of PMOS input transistors when the common-mode input voltage is significantly less than the cross-over voltage by:turning off the third PMOS transistor to allow the second current to flow through the second pair of PMOS input transistors to the second NMOS current mirror, which enables the second NMOS current mirror to generate the stolen current; and turning off the second PMOS transistor to cut off the stolen current and maintain the first current supplied to the first pair of PMOS input transistors.
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