In some cases, a single stage of gain may not be enough, and a second stage may be cascaded with the first stage to produce a two-stage operational amplifier with a sufficient amount of gain. FIG. 3 (Prior Art) is a simplified circuit diagram of a two-stage operational amplifier 300 with Miller compensation. If Miller compensation is used, the dominant pole comes from the compensation capacitor (CC) and the non-dominant pole comes from the load capacitor (CL) located at the output of the second stage. The unity-gain bandwidth (UGB) of the operational amplifier 300 is ωu=gm1/CC, and thus, is dependent on the transconductance (gm1) of the first input stage. To ensure 60° phase margin (i.e., lowest power solution), the transconductance (gm2) of the second stage and the location of the second pole, ω2=gm2/Cl, is set equal to twice the UGB of the first input stage (i.e., 2ωu). Unfortunately, when CMOS input stage 200 is used in the first stage of the two-stage operational amplifier 300 shown in FIG. 3 (Prior Art), the √{square root over (2)} increase in the first stage transconductance (gm1) at the Vcross boundary poses a problem in terms of phase margin.
