FIG. 4 (Prior Art) is a graph plotting phase margin and phase margin frequency (UGB) vs. common-mode input voltage for the two-stage operational amplifier 300 shown in FIG. 3 (Prior Art) when the CMOS input stage 200 shown in FIG. 2 (Prior Art) is used in the first stage of the amplifier. As shown in FIG. 4 (Prior Art), the √{square root over (2)} increase in g_m1 at the V_cross boundary causes an approximately 8° drop in phase margin from the desired 60° phase margin in the voltage region surrounding V_cross (e.g., 0.7 V). This drop in phase margin directly and negatively impacts the stability of the circuit.

One method to combat phase margin degradation in the first stage of a two-stage amplifier is to increase the transconductance (g_m2) of the second stage to provide a phase margin of, for example, 70°. For example, if CMOS input stage 200 is used in the first stage of the operational amplifier 300, and the phase margin degrades by approximately 8°, increasing the second stage transconductance (g_m2) should provide enough margin to maintain the desired 60° phase margin. However, increasing the second stage transconductance (g_m2) consumes more power, and thus, is not an acceptable solution in low-power amplifier designs and applications.