In some embodiments, the third PMOS transistor (P11) may be configured to prevent or allow the second current to flow through the second pair of PMOS input transistors (P9, P10) to the second NMOS current mirror (N9, N10), depending on whether the common-mode input voltage is greater than or less than the cross-over voltage. When the common-mode input voltage is significantly greater than the cross-over voltage, for example, the third PMOS transistor (P11) may turn on to prevent the second current from flowing through the second pair of PMOS input transistors (P9, P10) to the second NMOS current mirror (N9, N10), which prevents the second NMOS current mirror (N9, N10) from generating the stolen current. Thus, the stolen current is zero when the common-mode input voltage is greater than the cross-over voltage.

When the common-mode input voltage is significantly less than the cross-over voltage, the third PMOS transistor (P11) may turn off to allow the second current to flow through the second pair of PMOS input transistors (P9, P10) to the second NMOS current mirror (N9, N10), which enables the second NMOS current mirror (N9, N10) to generate the stolen current. However, the second PMOS transistor (P8) may turn off to cut off the stolen current when the common-mode input voltage is less than the cross-over voltage. Thus, the stolen current is zero when the common-mode input voltage is less than the cross-over voltage.