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CMOS input stage circuits and related methods

專利號
US10868505B1
公開日期
2020-12-15
申請人
Silicon Laboratories Inc.（US TX Austin）
發(fā)明人
Mohamed M. Elsayed; Sudipta Sarkar
IPC分類
H03F3/45
技術(shù)領(lǐng)域
pmos,vcross,input,nmos,current,voltage,pair,stage,transistor,cmos
地域： TX TX Austin

摘要

Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

說明書

As noted above, current steering circuit 560 is configured to steer the tail current (i.e., the first current, I1) to the NMOS input pair (N1, N2) and/or to the first PMOS input pair (P1, P2), depending on whether the common-mode input voltage is significantly greater than, significantly less than or substantially equal to the cross-over voltage (Vcross). When the common-mode input voltage is significantly less than Vcross, for example, the first PMOS transistor (P7) turns “off” to steer the tail current (I1) toward the first PMOS input pair (P1, P2) and turn “off” the NMOS input pair (N1, N2). When the common-mode input voltage is significantly greater than Vcross, the first PMOS transistor (P7) turns “on” to steer the tail current (I1) toward the NMOS input pair (N1, N2) and turn “off” the first PMOS input pair (P1, P2). When PMOS transistor P7 is “on,” the tail current (I1) flows through PMOS transistor P7 and is mirrored by the first NMOS current mirror (N7 and N8) to the source terminals of the NMOS transistors (N1, N2) in the NMOS input pair.

權(quán)利要求

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