When the common-mode input voltage is substantially equal to V_cross, the first PMOS transistor (P7) partially turns “on,” such that a first portion of the tail current (I₁) is supplied to the pair of NMOS input transistors (N1, N2) and a second portion of the tail current (I₁) is supplied to the first pair of PMOS input transistors (P1, P2). In some embodiments, the tail current (I₁) may be approximately equal to 2I. In such embodiments, less than one-half (I?I_steal/2) of the tail current may be supplied to the pair of NMOS input transistors (N1, N2), while the other half (I?I_steal/2) of the tail current is supplied to the first pair of PMOS input transistors (P1, P2) when the common-mode input voltage is substantially equal to V_cross.

As noted above, there is a wide range of voltages within the intermediate CMV region, which can be used to set V_cross and maximize either the operating range of the first PMOS input pair (P1, P2) or the operating range of the NMOS input pair (N1, N2). When relatively low voltages (e.g., voltages close to ground) are preferred, the operating range of the first PMOS input pair (P1, P2) can be maximized by setting V_cross close to V_DD (2V_Odp+|V_THp|), where V_Odp and |V_THp| are the over-drive voltage and threshold voltage respectively of the PMOS transistors. When relatively high voltages (e.g., voltages close to V_DD) are preferred, the operating range of the NMOS input pair (N1, N2) can be maximized by setting V_cross close to (2V_Odn+V_THn), where V_Odn and V_THn are the over-drive voltage and threshold voltage respectively of the NMOS transistors.