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CMOS input stage circuits and related methods

專利號
US10868505B1
公開日期
2020-12-15
申請人
Silicon Laboratories Inc.(US TX Austin)
發(fā)明人
Mohamed M. Elsayed; Sudipta Sarkar
IPC分類
H03F3/45
技術(shù)領(lǐng)域
pmos,vcross,input,nmos,current,voltage,pair,stage,transistor,cmos
地域: TX TX Austin

摘要

Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

說明書

It will be appreciated to those skilled in the art having the benefit of this disclosure that this disclosure is believed to provide various embodiments of improved CMOS input stage circuits and related methods to maintain a near constant transconductance (gm) across the entire common mode voltage (CMV) range, including within a near voltage region surrounding a cross-over voltage (Vcross) boundary between a low CMV region and a high CMV region of the CMV range. Further modifications and alternative embodiments of various aspects of the disclosure will be apparent to those skilled in the art in view of this description. For example, although the input stage circuits disclosed herein are implemented using CMOS technology, the disclosed input stage circuits could be alternatively implemented using other types of field effect transistors (FETs) or bipolar junction transistors (BJTs).

It is to be understood that the various embodiments of the disclosed CMOS input stage circuits shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the disclosed embodiments may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this disclosure. It is intended, therefore, that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

權(quán)利要求

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