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Biasing circuits for voltage controlled or output circuits

專利號
US10868507B2
公開日期
2020-12-15
申請人
Ronald Quan
發(fā)明人
Ronald Quan
IPC分類
H03G1/00; H03F3/45; H03F1/02; H03G3/30
技術領域
voltage,fet,q1b,amplifier,vds,drain,q1a,or,rfb,r7
地域： CA CA Cupertino

摘要

A number of biasing circuits for amplifiers including voltage controlled amplifier is presented. Also a number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.

說明書

G[(R7)/(R7+Rfb)]=?. Or in other words, [(R7+Rfb)/(R7)]=2 G, which equivalently states that (Rfb/R7)=2 G?1. For example if G=10 (e.g., R10/R11=9, such as R10=18 kΩ and R11=2 kΩ), then (Rfb/R7)=2×10?1=20?1=19 or (Rfb/R7)=19, which can have example values of:

Rfb=1900 kΩ (1.9 MΩ) and R7=100 kΩ. One other advantage to having R7<<Rfb due to G>1 is that the control voltage is almost completely coupled to the gate terminal of the FET Q3 (e.g., 1?1/(2 G); for example if G=10, the transferred voltage is 1?1/(2 G)=1?1/(2×10)=1?0.05=95% transferred to the gate of the FET, Q3.

In the FIGS. 3, 4, 5, 6, and 7A, the control voltage from the wiper or slider of VR1 is transferred to the gate at half or 50%. This results in that to provide a full range of attenuation, twice the voltage is required at the wiper of VR1. FIG. 7B with G>1 allows for less than twice the voltage at the wiper of VR1 to provide a full range of attenuation from the voltage controlled resistor FET.

權利要求

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