FIG. 11 shows an improved multiplier circuit from FIG. 10 by including amplifiers A13 and A7 to isolate the feedback resistors R13 and R7 from transferring any portion of the modulation signal or inverted modulation signal to the output of the multiplier circuit of FIG. 11. Multiplier linearity with JFETs or depletion mode FETs is improved by including amplifiers A13 that drives feedback resistor R13, and (amplifier) A7 that drives feedback resistor R7. Multiplier linearity improvement is provided more so by including amplifiers A13 that drives feedback resistor R13, and (amplifier) A7 that drives feedback resistor R7 when the FETs (e.g., Q1A and Q1B) are enhancement mode FETs or MOSFETs (e.g., when compared to using enhancement mode devices in FIG. 10 with bias ?v→+v for a positive bias voltage, Vbias). Note with N Channel enhancement mode FETs, Vbias should be a positive voltage, that results in the voltage source ?v→+v coupled to VR1.
