FIG. 12 shows a voltage controlled phase shifting circuit via U1B with linearized drain to source Q2B FET resistance (e.g., via feedback network Rfb and R16). A buffer amplifier U1A is included to avoid or to prohibit leaking the phase modulation or phase shifting signal (e.g., Vphase_mod may include an AC and or DC signal(s)) into the output terminal Vout. The phase shift is related to the time constant of C14×RdsQ2B∥R19, where RdsQ2B is the drain to source resistance of FET Q2B, and where RdsQ2B∥R19=[(RdsQ2B×R19)/(RdsQ2B+R19)]. In this example of FIG. 11, the phase shift=180 degrees?2 arctan(f/fc). Where f=frequency from the Vin signal source, and fc=1/[2π(C14×RdsQ2B∥R19)]. In some circuits R19 may be omitted such that R19=infinite ohms. Although Q2B in FIG. 12 is shown as a JFET or depletion mode FET, Q2B may include an enhancement mode FET or MOSFET as shown in FIG. 13.
