FIG. 18 shows another embodiment with further improvement wherein the FET circuits include feedback linearization (e.g., reduction of distortion) from the drain to source resistances of Q1A and Q1B via amplifiers and feedback networks. A first FET (e.g., Q1A) is supplied with an in-phase input signal Vin; a second FET (e.g., Q1B) is supplied with an out of phase (e.g., inverted phase) input signal via the output of U1B. Each FET includes a distortion reduction circuit via U1A, Rfb1, and Ra1 for Q1A, and a distortion reduction circuit via U2A, Rfb2, and Rb1 for Q1B. The signals from the drains of Q1A and Q1B are coupled via U1A and U2A to a differential amplifier U2B to further subtract or cancel even order distortion. The output signal is coupled to an output terminal of U2B. A bias voltage to the FET is provided by VR1, which is a negative voltage for N channel depletion mode FETs or N channel JFETs. Preferably Q1A and Q1B are matched.
