FIG. 20 shows a bias servo system to automatically adjusting an FET to a predetermined drain to source resistance. In this example circuit, a reference FET, Q1B, is operating in the ohmic or triode region (e.g., not in the current source region nor in the FET's saturation region). A reference voltage, Vref, such as 0.1 volt DC (although other reference voltages may be used) is coupled to a load resistor R6, which by example is 10 KΩ in this circuit but other values of R6 may be used. The reference voltage is coupled to VR2, which can be adjusted to bias Q1B to a predetermined drain to source resistance. VR2's wiper or slider terminal couples a voltage Vref_2 to the (?) input of amplifier U3A, which by negative feedback forces the (+) input to the same voltage, Vref_2, as the (?) input terminal. The output of the amplifier U3A will then provide a voltage, Vbias′, at the gate of the FET Q1B such that the drain voltage equals Vref_2. For example, if the drain to source resistance of Q1B is to be set to equal R6 such as 10 KΩ, the drain voltage at Q1B will be 50% of Vref or the drain voltage at Q1B=50% of 0.1 volt=0.05 volt or +50 mV DC at the drain of Q1B. VR2 is then set or adjusted to provide Vref_2=+50 mV DC. Of course other values of Vref_2 can be set by VR2 to provide other values of the drain to source resistance of Q1B. With Q1A being substantially matched to Q1B, the same gate voltage, Vbias′, is provided or supplied to the gate of Q1A via amplifier A102 (e.g., unity gain amplifier) and R1 (e.g., R1=10 KΩ, but other resistance values may be used), which then provides the same drain to source resistance (e.g., 10 KΩ in this example; or other resistance values may be predetermined) as Q1B. FIG. 20 shows an example voltage controlled attenuator via Vin, C8, Rs, Q1A, A101, and Vout. Other circuits such as phase shifter and or gyrator circuits previous shown or mentioned may include the Q1A FET or the FIG. 20 circuit for providing a predetermined drain to source resistance. One novel aspect of FIG. 20 is that regardless of which part number, batch, or production run of matched FETs (e.g., for Q1A and Q1B) are used that have varying pinch off voltages Vp or drain current IDSS specifications, this circuit will provide automatic biasing to the gate of the FET for a predetermined drain to source resistance. Note that two or more matched FETs may be used to provide one or more matched predetermined drain to source resistance. For example, if reference FET Q1B were matched to a Q1A, Q1C, Q1D, . . . and so on, the FETs Q1A, Q1C, Q1D, . . . and so on will have the same drain to source resistance as reference FET Q1B (e.g., via Vbias′).
