In the following example circuits including FIGS. 1, 2, 3, 4, 5, 6, 7A, 7B, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, and or 22 other values for resistors, capacitors, op amps, FETs (e.g., depletion and or enhancement field effect transistor(s)), currents and or voltages may be used.
FIG. 1 shows a prior art voltage controlled resistor circuit where the field effect transistor Q1 is a depletion mode device. Although junction field effect transistors are generally depletion devices, there are some (but not a majority of) insulated gate or MOS (Metal Oxide Silicon) field effect transistors that are also depletion type devices. However, the majority or MOS field effect transistors (MOSFET) are enhancement mode devices.
In FIG. 1 the gate to source voltage of the FET Q1 is varied by variable resistor or variable voltage divider VR1 that provides a voltage range from 0 volts for minimum drain to source resistance to a negative voltage that provides a near open circuit resistance (e.g., very high or close to infinite resistance) across the drain and source of the FET Q1. At 0 volts gate to source voltage maximum attenuation occurs via input source resistor R1. And at a negative gate to source voltage where the drain to source resistance is nearly infinite resistance, the input signal Vin passes virtually completely (e.g., with minimum attenuation) to the output terminal Vout.
All field effect transistors have a source terminal (e.g., denoted by “S”), a gate terminal (e.g., denoted by “G”), and a drain terminal (e.g., denoted by “D”). An FET's resistance is taken across the drain and source terminals.
