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Biasing circuits for voltage controlled or output circuits

專利號
US10868507B2
公開日期
2020-12-15
申請人
Ronald Quan
發(fā)明人
Ronald Quan
IPC分類
H03G1/00; H03F3/45; H03F1/02; H03G3/30
技術(shù)領(lǐng)域
voltage,fet,q1b,amplifier,vds,drain,q1a,or,rfb,r7
地域: CA CA Cupertino

摘要

A number of biasing circuits for amplifiers including voltage controlled amplifier is presented. Also a number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.

說明書

Where IDSS is the maximum drain current when the gate to source voltage, Vgs=0 volt and where the cut-off voltage or pinch off voltage is Vp, which is a constant given by the data sheet of the depletion mode FET, and where Vds=drain to source voltage, and where the control voltage, Vgs, is the gate to source voltage that varies the drain to source resistance of the depletion mode FET.

A general equation for a depletion mode FET resistance from its drain to source terminals, Rds, such is characterized by the following equation:

R ds = 1 / { I DSS ? [ - 2 ? ( 1 Vp ) ? ( 1 - Vgs Vp ) - 2 ? ( Vds Vp ) ?

權(quán)利要求

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