Logic cell structure and integrated circuit with the logic cell structure
地域：
Hsinchu
摘要
A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.
說明書
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Typically, in the design of integrated circuits, standard cells having fixed functions are pre-designed. The pre-designed standard cells are stored in cell libraries. When designing integrated circuits, the standard cells are retrieved from the cell libraries and placed into desired locations on an integrated circuit layout. During the cell placement, the unit-row height layout system or the mixed-row heights system may be used. However, it is very challenging for the designer to balance the cell delay and the placement density of logic cells in the unit-row height layout system or the mixed-row heights system. Therefore, a novel architecture of logic cell for improving the cell placement problem in the layout system is highly desirable in the field of IC (Integrated circuit) design.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權(quán)利要求
What is claimed is:1. A logic cell structure embodied on a non-transitory computer-readable medium, the logic cell structure comprising:a first portion arranged to be a first layout of a first semiconductor element formed in front-end-of-line (FEOL), wherein the logic cell structure is formed on a substrate area; as viewed from a top of the substrate area, the first portion is placed in a first cell row of the substrate area, the first cell row extends in a first direction, and the first portion has a first height in a second direction vertical to the first direction; a second portion arranged to be a second layout of a second semiconductor element formed in FEOL, wherein as viewed from the top of the substrate area, the second portion is placed in a second cell row of the substrate area and has the first height in the second direction, and the first portion is separated from the second portion; and a third portion, arranged to be a third layout of an interconnecting path formed in back-end-of-line (BEOL), the interconnecting path formed according to the third portion being at a level higher than each of the first semiconductor element formed according to the first portion and the second semiconductor element formed according to the second portion, the interconnecting path being used for coupling the first semiconductor element and the second semiconductor element, wherein as viewed from the top of the substrate area, the third portion is placed within the substrate area, and at least a part of the third portion is placed between the first cell row and the second cell row. 2. The logic cell structure of claim 1 , wherein the third portion is arranged to be a second height, and the second height is different from the first height. 3. The logic cell structure of claim 2 , wherein the first height is greater than the second height. 4. The logic cell structure of claim 2 wherein the second height is greater than the first height. 5. The logic cell structure of claim 1 , wherein an upper boundary of the third portion is abutted against a lower boundary of the first portion, and a lower boundary of the third portion is abutted against an upper boundary of the second portion. 6. The logic cell structure of claim 1 , wherein an operating speed of a transistor included in the first semiconductor element formed according to the first portion is equal to an operating speed of a transistor included in the second semiconductor element formed according to the second portion. 7. The logic cell structure of claim 1 , wherein the first portion, the second portion, and the third portion are arranged to be a same width. 8. The logic cell structure of claim 1 , wherein the first portion, the second portion, and the third portion are bounded by a bounding box with a height and a width, the first portion and the second portion are located on a diagonal direction of the bounding box, and the third portion is arranged to interconnect the first portion and the second portion within the bounding box. 9. The logic cell structure of claim 8 , wherein the height is not less than a total of the first height of the first portion, the first height of the second portion, and a distance between the first portion and the second portion in the second direction. 10. The logic cell structure of claim 8 , wherein the width is not less than a total of a first width of the first portion, a second width of the second portion, and a distance between the first portion and the second portion in the first direction. 11. An integrated circuit, comprising:a substrate area, comprising:a first doped row, wherein as viewed from a top of the substrate area, the first doped row extends in a first direction, and has a first height in a second direction vertical to the first direction; a second doped row, wherein as viewed from the top of the substrate area, the second doped row extends in the first direction, and has the first height in the second direction; and a third doped row, wherein as viewed from the top of the substrate area, the third doped row has a second height in the second direction, an upper edge of the third doped row abuts against a lower edge of the first doped row, and a lower edge of the third doped row abuts against an upper edge of the second doped row; a first logic cell, formed on the substrate area, the first logic cell comprising:a first portion, wherein as viewed from the top of the substrate area, the first portion has the first height in the second direction, and placed in the first doped row; a second portion, wherein as viewed from the top of the substrate area, the second portion has the first height in the second direction, and placed in the second doped row; and a third portion, arranged to couple the first portion and the second portion, wherein as viewed from the top of the substrate area, the third portion is placed between the first doped row and the second doped row; and a second logic cell, placed in the third doped row, wherein as viewed from the top of the substrate area, the third portion is overlapped with the second logic cell. 12. The integrated circuit of claim 11 , wherein the third portion with the second height is overlapped with the third doped row, and the first height is greater than the second height. 13. The integrated circuit of claim 11 , wherein the third portion with the second height is overlapped with the third doped row, and the second height is greater than the first height. 14. The integrated circuit of claim 11 , wherein the first portion, the second portion, and the third portion are arranged to be a same width. 15. The integrated circuit of claim 11 ,wherein the third portion is arranged to bridge over the second logic cell placed in the third doped row. 16. An integrated circuit, comprising:a substrate area, comprising:a first doped row, wherein as viewed from a top of the substrate area, the first doped row extends in a first direction, and has a first height in a second direction vertical to the first direction; a second doped row, wherein as viewed from the top of the substrate area, the second doped row extends in the first direction, and has the first height in the second direction; and a third doped row, wherein as viewed from the top of the substrate area, the third doped row has a second height in the second direction, an upper edge of the third doped row abuts against a lower edge of the first doped row, and a lower edge of the third doped row abuts against an upper edge of the second doped row; a logic cell, formed on the substrate area, the logic cell comprising:a first portion, wherein as viewed from the top of the substrate area, the first portion has the first height in the second direction, and placed in the first doped row; a second portion, wherein as viewed from the top of the substrate area, the second portion has the first height in the second direction, and placed in the second doped row; and a third portion, wherein as viewed from the top of the substrate area, the third portion is overlapped with an upper edge and the lower edge of the first doped row, the upper edge and a lower edge of the second doped row, and the third doped row, for interconnecting the first portion and the second portion. 17. The integrated circuit of claim 16 , wherein the second height is different from the first height. 18. The integrated circuit of claim 16 , wherein the logic cell is bounded by a bounding box with a height and a width, the first portion and the second portion are located on a diagonal direction of the bounding box, and the third portion is an interconnecting path used for interconnecting the first portion and the second portion within the bounding box. 19. The integrated circuit of claim 18 , wherein the height is not less than a total of the first height of the first portion, the first height of the second portion, and a distance between the first portion and the second portion in the second direction. 20. The integrated circuit of claim 18 , wherein the width is not less than a total of a first width of the first portion, a second width of the second portion, and a distance between the first portion and the second portion in the first direction.
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