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Logic cell structure and integrated circuit with the logic cell structure

專利號
US10868538B1
公開日期
2020-12-15
申請人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.(TW Hsinchu)
發(fā)明人
Shao-Huan Wang; Chun-Chen Chen; Sheng-Hsiung Chen; Kuo-Nan Yang
IPC分類
H03K19/17704; H01L23/528; H03K19/17736; H01L27/02; G06F30/392
技術(shù)領(lǐng)域
doped,cell,logic,row,portion,layout,rows,second,first,in
地域: Hsinchu

摘要

A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.

說明書

According to some embodiments, the height S1 of the third portion 310c may be greater than the height S. The height S1 may be a total of n*S and m*T, wherein n is an integer not less than 2, and m is an integer not less than 1. For example, the height S1 may be a total of 2*S and 1*T. In this example, the height S1 is substantially equal to a total of the heights S of two standard cell structure 304 and the height of one standard cell structure 306.

權(quán)利要求

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