As the row height T of the second-type doped rows 404a-404d is greater than the row height S of the first-type doped rows 402a-404d, the second-type doped rows 404a-404d may be configured to have relatively high speed transistors (or semiconductor elements), and the first-type doped rows 402a-402d may be configured to have relatively low speed transistors.
According to some embodiments, a logic cell 402 with the cell structure 304 may be placed on the first-type doped rows 402d. A logic cell 404 with the cell structure 306 may be placed on the second-type doped rows 404c.