Logic cell structure and integrated circuit with the logic cell structure
摘要
說明書
According to some embodiments, a plurality of relatively low speed logic cells 506a-506e may be placed on the first-type doped rows 502a-502d respectively, and a plurality of relatively high speed logic cells 508a-508f may be placed on the second-type doped rows 504a-504d respectively. The number and the size of the logic cells 506a-506e may be different from the number and the size of the logic cells 508a-508f. Therefore, after the cell placement operation, the usage of the first-type doped rows 502a-502d and the second-type doped rows 504a-504d may be unbalanced. For example, the usage rate of the first-type doped rows 502a-502d may be 30% while the usage rate of the second-type doped rows 504a-504d may be 70%. The unused spaces, e.g. 510a-510c, in the first-type doped rows 502a-502d are wasted but the area is still counted for the layout system 500a. To increase the usage rate of the first-type doped rows 502a-502d, the logic cells with the cell structure 308 may be placed in the spaces 510a-510c of the first-type doped rows 502a-502d as shown in
