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Logic cell structure and integrated circuit with the logic cell structure

專利號
US10868538B1
公開日期
2020-12-15
申請人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.（TW Hsinchu）
發(fā)明人
Shao-Huan Wang; Chun-Chen Chen; Sheng-Hsiung Chen; Kuo-Nan Yang
IPC分類
H03K19/17704; H01L23/528; H03K19/17736; H01L27/02; G06F30/392
技術(shù)領(lǐng)域
doped,cell,logic,row,portion,layout,rows,second,first,in
地域： Hsinchu

摘要

A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.

說明書

FIG. 9C is a diagram illustrating of the logic cell 912 placed in the mixed-row heights layout system 900 in accordance with some embodiments. When the logic cell 902 is replaced with the logic cell 912, the logic cell 902 may be re-configured into two portions, i.e. 912a and 912b. The two portions 912a and 912b may be placed in the first-type doped rows 906 and 908 respectively. The logic cell 912 is similar to the above mentioned logic cell 512 or 514, thus the detailed description of the logic cell 912 is omitted here for brevity.

權(quán)利要求

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