Briefly, the proposed embodiment provides jump-row cell structures and rectilinear cell structures for the multi-height layout system to increase and to balance the usage density and the placement flexibility of the multi-height layout system. The resource of the multi-height layout system may be increased by placing the rectilinear cell structures into the rectilinear space fragments. Moreover, the jump-row logic cell structures may provide transistors with equal speed such that the signal delay of the cell may be balanced and optimized.

In some embodiments, the present disclosure provides a logic cell structure embodied on a non-transitory computer-readable medium. The logic cell structure comprises a first portion, a second portion, and a third portion. The first portion with a first height is arranged to be a first layout of a first semiconductor element. The second portion with the first height is arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.