In some embodiments, the present disclosure provides an integrated circuit. The integrated circuit comprises a first doped row, a second doped row, a third doped row, and a first logic cell. The first doped row is configured with a first height. The second doped row is configured with the first height. The third doped row is configured with a second height. An upper edge of the third doped row abuts against a lower edge of the first doped row, and a lower edge of the third doped row abuts against an upper edge of the second doped row. The first logic cell comprises a first portion, a second portion, and a third portion. The first portion with the first height is placed in the first doped row. The second portion with the first height is placed in the second doped row. The third portion is arranged to couple the first portion and the second portion.

In some embodiments, the present disclosure provides an integrated circuit. The integrated circuit comprises a first doped row, a second doped row, a third doped row, and a first logic cell. The first doped row is configured with a first height. The second doped row is configured with the first height. The third doped row is configured with a second height. An upper edge of the third doped row abuts against a lower edge of the first doped row, and a lower edge of the third doped row abuts against an upper edge of the second doped row. The logic cell comprises a first portion, a second portion, and a third portion. The first portion with the first height is placed in the first doped row. The second portion with the first height is placed in the second doped row. The third portion is overlapped with the first doped row, the second doped row, and the third doped row, for interconnecting the first portion and the second portion.