According to some embodiments, the operations 208?212 may be an APR (Automatic Place and Route) process. During the APR process, a layout of the semiconductor circuit (i.e. integrated circuit, IC) is generated automatically by the APR process by using the plurality of proposed standard cells or logic cells. A logic cell may represent a single functional block of logic. A standard cell for example may represent a NAND gate, NOR gate, flip flop, AND gate, OR gate, XOR gate, XNOR gate, inverter, latch, or the like. The logic cell enables an integrated circuit designer to utilize a library of cells as reusable building blocks for an integrated circuit without the need to separately design each block of logic represented by a cell. The logic cells may be included in a library of cells for use by integrated circuit designers.

FIG. 3 is a diagram illustrating a cell library 302 for storing logic cells in accordance with some embodiments. The cell library 302 may be a standard cell library. The logic cells may be standard cells, and the logic cells may be applied into cell rows of a layout of a semiconductor circuit during the operations 208?212 or the APR process. A logic cell is arranged to perform a specific logical function. For example, the specific logical function may be the operation of NAND, NOR, flip flop, AND, OR, XOR, XNOR, inverting, latching, or the like. The logic cells may have different cell structures. According to some embodiments, the logic cells may be implemented with a plurality of cell structures 304, 306, 308, 310, 312, and 314. It is noted that the present disclosure is not limited by those cell structures. The logic cells may be configured to have other type of cell structures.