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Logic cell structure and integrated circuit with the logic cell structure

專利號
US10868538B1
公開日期
2020-12-15
申請人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.(TW Hsinchu)
發(fā)明人
Shao-Huan Wang; Chun-Chen Chen; Sheng-Hsiung Chen; Kuo-Nan Yang
IPC分類
H03K19/17704; H01L23/528; H03K19/17736; H01L27/02; G06F30/392
技術(shù)領(lǐng)域
doped,cell,logic,row,portion,layout,rows,second,first,in
地域: Hsinchu

摘要

A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.

說明書

According to some embodiments, the cell structure 304 may be a standard cell structure with a first cell height S. The cell structure 306 may be a second standard cell structure with a second cell height T. The cell height T is greater than the cell height S. The widths of the cell structure 304 and 306 are W_a and W_b respectively. According to some embodiments, the cell heights S and T may be constant heights and the widths W_a and W_b may be a variable width. However, this is not a limitation of the present disclosure. In another embodiment, the cell heights S and T may be variable heights and the widths W_a and W_b may be a constant width.

權(quán)利要求

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