In single-read RQL D-register circuit 700, Josephson junction J2 junction triggers when the logical lock input LCLK goes “high” (i.e., when a positive SFQ pulse is provided on the logical clock input LCLK to assert the logical clock input), bringing the superconducting phase of Josephson junction J2 to 2π radians (“high”). The phase of Josephson junction J2 remains “high” if the data input DI is asserted (i.e., with a positive SFQ pulse introduced to data input DI) upon the falling edge of the logical clock signal provided on input LCLK. Josephson junction J2 will “flip back” (i.e., its phase will return to 0 radians, “l(fā)ow”) if data input DI is unasserted (“l(fā)ow”) during this time. Consequently, the superconducting phase of Josephson junction J2 determines the internal state of the body 702 of RQL D-register circuit 700. Thus, for example, Josephson junction J2 having a 2π radian superconducting phase can correspond to a stored “1” (logical “high”) value, whereas Josephson junction J2 having a 0 radian superconducting phase can correspond to a stored “0” (logical “l(fā)ow”). In particular, the stored state corresponds to the phase of state-storing Josephson junction J2 during the latter half of an operation cycle, as can be noted in timing diagram 1000, particularly during “write 0” operations.