A stored “1” from a triggered Josephson junction J2 in body 702 provides a pre-critical bias current to Josephson junction J5 in tail 704. Under this biased condition, tail Josephson junction J5 does not trigger unless the read-enabling input NDRO is asserted (goes “high”), which then passes the body-stored state to output QO. The triggering of Josephson junction J5 does not affect the internal state of the body 702 (encoded as the superconducting phase of Josephson junction J2), giving the readout of circuit 700 its non-destructive property.

Because tail Josephson junction J5 can only trigger when body-state storage Josephson junction J2 has triggered to bring it into its 2π radian superconducting phase and the non-destructive readout input NDRO is asserted with a positive SFQ pulse, the NDRO input and corresponding output QO can be either wave-pipelined logic (WPL) or phase-mode logic (PML) encoded, and the assertion of the non-destructive readout input NDRO must arrive after Josephson junction J2 has been properly setup or logical clock signal provided on input LCLK is de-asserted. With proper phase timing of the logical lock and non-destructive readout signals provided on inputs LCLK and NDRO, data can be written and read during the same clock cycle, speeding memory and computing operations.

The various operational states of circuit 700 will now be explored with reference to the simulation timing diagram 1000 of FIG. 10, reading its operation cycles (separated by vertical broken lines) in chronological order from left to right.