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Superconducting non-destructive readout circuits

專利號
US10868540B2
公開日期
2020-12-15
申請人
Anna Y. Herr; Quentin P. Herr; Ryan Edward Clarke; Harold Clifton Hearne, III; Alexander Louis Braun; Randall M. Burnett; Timothy Chi-Chao Lee(US VA Falls Church)
發(fā)明人
Anna Y. Herr; Quentin P. Herr; Ryan Edward Clarke; Harold Clifton Hearne, III; Alexander Louis Braun; Randall M. Burnett; Timothy Chi-Chao Lee
IPC分類
H03K19/195; G11C11/44; H03K3/38; G06N10/00
技術(shù)領(lǐng)域
josephson,ndro,rql,junction,lclk,input,circuit,tail,j2,logical
地域: MD MD Ellicott City

摘要

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

說明書

Latches and flip-flops are circuits that can be used to store state information and to change state by signals applied to one or more control inputs. In modern computing and communications electronics, these are basic storage elements in memories and sequential logic. A latch is asynchronous, with its output changing as soon as its data input does (or at least after a small propagation delay), provided the latch is enabled via an enable input. A flip-flop is synchronous and edge-triggered and only changes state when a clocking control signal goes from high to low or low to high. Thus, a conventional D flip-flop, e.g., one implemented in CMOS, has two binary inputs, a data input D and a clock input, and at least one output, Q. The D flip-flop captures the value of the D input at a definite portion of an input clock cycle, e.g., a rising edge or a falling edge, known as the capture time. That captured value becomes the Q output. The output Q does not change except at the capture time (or some small propagation delay thereafter). In practical implementations it is required that a data input D be stable for some setup time prior to the capture time and for some hold time after the capture time for the input to be reliably captured and propagated to the output. A conventional D latch, with an enable input rather than a clock input, behaves similarly, except that the output can change according to the data input so long as an enable input remains asserted.

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