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Superconducting non-destructive readout circuits

專利號
US10868540B2
公開日期
2020-12-15
申請人
Anna Y. Herr; Quentin P. Herr; Ryan Edward Clarke; Harold Clifton Hearne, III; Alexander Louis Braun; Randall M. Burnett; Timothy Chi-Chao Lee(US VA Falls Church)
發(fā)明人
Anna Y. Herr; Quentin P. Herr; Ryan Edward Clarke; Harold Clifton Hearne, III; Alexander Louis Braun; Randall M. Burnett; Timothy Chi-Chao Lee
IPC分類
H03K19/195; G11C11/44; H03K3/38; G06N10/00
技術(shù)領(lǐng)域
josephson,ndro,rql,junction,lclk,input,circuit,tail,j2,logical
地域: MD MD Ellicott City

摘要

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

說明書

FIG. 17 provides an AND gate circuit 1700 according to the body-tail topology described herein, where the body stage is reduced to a single input B and associated inductor L1 and Josephson junction J2, which body stage supplies a pre-critical bias current to tail stage Josephson junction J5 via linking inductor LL. With a positive SFQ pulse at input A to assert that input, Josephson junction J5 triggers and produces an output of “1” at output Z, fulfilling the AND logical function of Z=A AND B.

FIG. 18 provides an A-NOT-B gate circuit 1800 sharing structural similarities to the multiplexer circuit 1400 described previously. The upper-right portion of the circuit provides a pulse generator signal, indicated in FIG. 18 as “PULSE GEN.,” as a return-to-zero (RZ) tie-high signal. When combined with an assertion signal (“1”) provided at input B, the pulse generator signal causes escape Josephson junction J3 to trigger, thereby starving tail Josephson junction J5 of a pre-critical bias current that would otherwise allow SFQ pulses provided at input A to propagate to output Z. Thus, when input B is “high,” input A pulses are blocked. In absence of a “1” on input B, circuit 1800 allows for the pulse generator to provide the requisite pre-critical bias current to tail Josephson junction J5, thereby activating input A to trigger tail Josephson junction J5 and thus produce a “1” at the output Z.

權(quán)利要求

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