Thus, FIG. 21 shows an example of an array 2100 of multi-tail NDRO gates 2102 arranged as memory or logic elements, each of which can correspond, for example, to any of circuits 100, 900, 1200, or a multi-tail version of circuit 1300 as described above. Each gate 2102 can have a body B and multiple tails T. Read lines are illustrated as solid and write lines are illustrated as dashed. Word lines are illustrated as thin horizontal lines and bit lines are illustrated as thick vertical lines. Word read enable lines 2104 are represented as thinner solid lines each connecting to the NDRO inputs of tails T in a row. Word write enable lines 2106 are represented as thinner broken lines each connecting to the LCLK inputs of bodies B in a row. Bit read data lines 2108 are represented as thicker solid lines each connecting to the QO outputs of tails T in a column. Bit write data lines 2110 are represented as thicker broken lines each connecting to the DI inputs of bodies B in a column. While the bit lines are defined as columns and word lines as rows in this particular image, this arrangement is arbitrary and could be reversed. Other connections (e.g., for AC clocks or ground) are omitted from FIG. 21 for clarity. The array 2100 can be of any suitable size (i.e., having any number of columns and rows), and can be used as a memory or as a logic array, e.g., a programmable logic array (PLA) or field-programmable gate array (FPGA) to output evaluated logic functions. In the illustrated example of FIG. 21, two word read enable lines 2104 are associated with each row of NDRO gates 2102 and two bit read data lines 2108 are associated with each column of NDRO gates 2102, but the number of such lines can correspond to the number of tails in each NDRO gate 2102 and thus can be fewer or greater than two.