Yet another example includes an RQL central processing unit (CPU) that includes a register file having an array of RQL non-destructive readout (NDRO) gate circuits. Each NDRO gate circuit includes a body circuit having one of a D latch or a D flip-flop configured to store a logical state. Each body circuit is connected to at least two tail circuits in the NDRO gate circuit and is configured to supply a pre-critical state current to a respective tail Josephson junction in each of the at least two tail circuits. Each pre-critical state current is representative of the same stored logical state. Each tail circuit is configured to propagate to an NDRO output port of the respective tail circuit an output signal corresponding to the logical AND of the stored logical state with a respective NRDO read enable signal provided to an NDRO input port of the respective tail circuit. The propagation of any output signal from any of the tail circuits does not affect the logical state stored in the body circuit connected to said tail circuits. Each body circuit in the register file array of NDRO gate circuits can include a data input port and a logical clock input port. Word lines of the register file can be connected to the logical clock input ports of the body circuits across word-lines of the respective NDRO gate circuits in the array, and bit lines of the register file can be connected to the NDRO inputs of the tail circuits of the NDRO gate circuits in the array. Each NDRO gate circuit in the array can be configured to have its logical state both writable and readable in the same operation cycle.