The ADC 230 is coupled to the amplifier circuit 220 to receive the amplified signal 221, and is configured to convert the amplified signal 221 to a n-bit digital code 231 (or a digital code D_LSB). In other words, the n-bit digital code 231 is a digital representation of the amplified signal 221. The digital code D_LSB may be used to generate the multi-bit digital output D_OUT, in which the digital code D_LSB may be n least significant bits (e.g., n-bits that is closest to, and including, the LSB) of the multi-bit digital output D_OUT.

The control logic 240 is coupled to the ADC 230 to control the operation of the ADC 230 to generate the n-bit digital code 231. In an example, the ADC 130 may be or may include a successive approximation resister (SAR) ADC; and the control logic 240 may include a comparator and logic circuits that cooperate with the SAR ADC 230 to generate the n-bit digital code 231 from the amplified signal 221.

In some embodiments, the feedback circuit 250 may generate a m-bit digital code D_MSB based on the input signal I_IN. The control logic 240 may be coupled to the feedback circuit 250 to control the operations of the m-bit digital code D_MSB through the signal 241. In some embodiments, the m-bit digital code D_MSB may be combined with another digital code (e.g., n-bit digital code D_LSB) to generate the multi-bit digital output D_OUT. In some embodiments, the m-bit digital code D_MSB may be m most significant bits (e.g., m-bits that is closest to, and including, the MSB).