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Methods and apparatus for a delta-sigma analog-to-digital converter

專利號
US10868564B1
公開日期
2020-12-15
申請人
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC（US AZ Phoenix）
發(fā)明人
Masayuki Kanematsu
IPC分類
H03M3/00; H03M1/12
技術領域
integrator,capacitor,adc,amplifier,signal,may,converter,first,delta,sigma
地域： AZ AZ Phoenix

摘要

Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.

說明書

1 2 3 4 5 6 7 8 9 10
BACKGROUND OF THE TECHNOLOGY

Analog-to-digital converters (ADCs) are utilized in a variety of electronic devices and systems to transform an analog signal to a digital signal. One ADC architecture commonly used is the delta-sigma type ADC. The delta-sigma ADC typically provides a sample-and-hold circuit as a first input stage. The sample-and-hold circuit occupies a large area on the ADC chip.

SUMMARY OF THE INVENTION

Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

A more complete understanding of the present technology may be derived by referring to the detailed description when considered in connection with the following illustrative figures. In the following figures, like reference numbers refer to similar elements and steps throughout the figures.

FIG. 1 is a block diagram of an incremental delta-sigma ADC in accordance with an exemplary embodiment of the present technology;

FIG. 2 is a partial circuit diagram of the incremental delta-sigma ADC in a hold mode and in accordance with an exemplary embodiment of the present technology;

權利要求

1
The invention claimed is:1. An incremental delta-sigma analog-to-digital converter (ADC), comprising:a sample-and-hold circuit comprising a first switch, a second switch, a first capacitor, and an amplifier; andan integrator comprising the first capacitor, a second capacitor, and the amplifier;wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.2. The incremental delta-sigma ADC according to claim 1, further comprising a digital-to-analog converter connected to the integrator.3. The incremental delta-sigma ADC according to claim 1, wherein the first capacitor is directly connected between the first switch and an input terminal of the amplifier.4. The incremental delta-sigma ADC according to claim 1, wherein the second switch is directly connected to the first capacitor and an output terminal of the amplifier.5. The incremental delta-sigma ADC according to claim 1, wherein the second capacitor is directly connected between the first switch and an output terminal of the amplifier.6. The incremental delta-sigma ADC according to claim 1, wherein the integrator further comprises a resistor:directly connected in series with the first capacitor anddirectly connected to the first switch.7. The incremental delta-sigma ADC according to claim 1, wherein the first switch is connected in series with the second capacitor.8. The incremental delta-sigma ADC according to claim 1, wherein the first capacitor is connected in series with the amplifier.9. The incremental delta-sigma ADC according to claim 1, wherein the second switch is connected in parallel with the amplifier.10. A method for operating on an input signal with a delta-sigma analog-to-digital converter (ADC), wherein the input signal has a voltage, comprising:sampling the input signal comprising closing a first switch and a second switch;charging a first capacitor to the voltage of the input signal;holding the charge of the first capacitor comprising:opening the first switch and second switch; andapplying a high impedance to the first capacitor using an amplifier; andsumming an output voltage from a signal converter and the voltage of the first capacitor;integrating the summed voltage using a second capacitor in parallel with the amplifier.11. The method according to claim 10, wherein the first capacitor is connected directly between the first switch and an input terminal of the amplifier.12. The method according to claim 10, wherein the second switch is connected in parallel with the amplifier.13. The method according to claim 10, wherein the first switch is connected in series with the second capacitor.14. A system configured to receive an input signal having a voltage, comprising:a sample-and-hold circuit comprising a first switch, a second switch, a first capacitor, and an amplifier, and configured to:receive the input signal;sample the input signal comprising operating the first switch and the second switch;charge the first capacitor to the voltage of the input signal;hold the charge of the first capacitor comprising:operating the first switch and second switch; andapplying a high impedance to the first capacitor using the amplifier; anda first integrator comprising the first capacitor, a second capacitor, and the amplifier, and configured to integrate a summed voltage using the second capacitor and the amplifier, wherein the summed voltage is a sum of an output voltage of a digital-to-analog converter and the voltage of the first capacitor;wherein the sample-and-hold circuit and the first integrator share the first capacitor and the amplifier.15. The system according to claim 14, wherein the first capacitor is directly connected between the first switch and an input terminal of the amplifier.16. The system according to claim 14, wherein the second switch is:directly connected to the first capacitor and an output terminal of the amplifier; and is connected in parallel with the amplifier.17. The system according to claim 14, wherein the first switch is connected in series with the second capacitor.18. The system according to claim 14, wherein the second capacitor is directly connected between the first switch and an output terminal of the amplifier.19. The system according to claim 14, wherein the amplifier comprises a p-channel transistor connected in series with an n-channel transistor.20. The system according to claim 14, further comprising a second integrator connected to an output terminal of the first integrator.
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