Referring to FIG. 1, the delta-sigma ADC 100 may be configured as a continuous-time incremental delta-sigma ADC to convert an analog input signal VIN into a digital output signal VOUT. The analog input signal VIN may be a continuously varying signal. In an exemplary embodiment, the delta-sigma ADC may comprise a sample-and-hold circuit 105, a first integrator 110, a second integrator 115, a first signal converter 120, and a second signal converter 125.
The sample-and-hold circuit 105 may be configured to receive and sample the input signal VIN and hold (lock) the sampled value at a constant level for a specified period of time. In an exemplary embodiment, and referring to FIG. 2, the sample-and-hold circuit 105 may comprise a first switch 225 directly connected to an input terminal 245, where the input terminal 245 receives the input signal VIN. The first switch 225 may comprise any circuit and/or device suitable for connecting and disconnecting the input terminal 245 from the remaining delta-sigma ADC 100. For example, the first switch 225 may comprise a transistor responsive to a control signal (not shown).
The sample-and-hold circuit 105 may further comprise a first capacitor 210 comprising a first plate and a second plate. The first capacitor 201 may be connected to the first switch 225, wherein in the first switch 225 is connected between the input terminal 245 and the first plate of the first capacitor 210.
