The sample-and-hold circuit 105 may further comprise a second switch 230 directly connected to the second plate of the first capacitor 210. The second switch 230 may comprise any circuit and/or device suitable for connecting and disconnecting a conducting path connected to the second plate of the first capacitor 210.

The sample-and-hold circuit 105 may further comprise an amplifier 200. The amplifier 200 may comprise an input terminal connected to the second plate of the first capacitor 210, and an output terminal connected to the second integrator 115 and a buffer 140. The amplifier 200 may comprise any circuit and/or device suitable for amplifying the input signal V_IN. In one embodiment, and referring to FIG. 4, the amplifier 200 may be configured as an inverting amplifier comprising a PMOS transistor 410 connected in series with an NMOS transistor 415, wherein gates of each transistor is connected to the second plate of the first capacitor 210, and a source terminal of the PMOS transistor 410 is connected to a supply voltage V_DD. A source terminal of the NMOS transistor 415 may be connected to a reference voltage V_SS. In the present case, a node between the PMOS transistor 410 and NMOS transistor 415 provides the output terminal of the amplifier 200. In an exemplary embodiment, the second switch 230 may be connected in parallel with the amplifier—in other words, the second switch 230 may be connected to both the input and output terminals of the amplifier 200.