The second signal converter 125 may provide a feedback loop from an output terminal of the first signal converter 120 to the first integrator 110. As such, the second signal converter 125 may receive the digital output signal V_OUT as a feedback signal S_F. The feedback signal S_F may be used to control the output signal (voltage) of the second signal converter 125. According to an exemplary embodiment, the second signal converter 125 may comprise a digital-to-analog converter and generate an analog signal to be used by the first integrator 110. For example, the output voltage from the second signal converter 125 may be added to the voltage of the first capacitor 210.

In one embodiment, and referring to FIG. 4, the second signal converter 125 may comprise a PMOS transistor 400 connected in series with an NMOS transistor 405, wherein gates of each transistor is connected to the feedback signal S_F, and a source terminal of the PMOS transistor 400 is connected to the supply voltage V_DD. A source terminal of the NMOS transistor 405 may be connected to the reference voltage V_SS. In the present case, a node between the PMOS transistor 400 and NMOS transistor 405 provides the output terminal of the second signal converter 125.