白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Methods and apparatus for a delta-sigma analog-to-digital converter

專利號
US10868564B1
公開日期
2020-12-15
申請人
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC(US AZ Phoenix)
發(fā)明人
Masayuki Kanematsu
IPC分類
H03M3/00; H03M1/12
技術領域
integrator,capacitor,adc,amplifier,signal,may,converter,first,delta,sigma
地域: AZ AZ Phoenix

摘要

Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.

說明書

1 2 3 4 5 6 7 8 9 10

In operation, the delta-sigma ADC 100 may perform a sample-and hold function and an integration function in sequence. For example, and referring to FIGS. 2 and 3, during the sample-and hold function, the first switch 225 and the second switch 230 are closed (ON). While the first and second switches 225, 230 are closed, the first capacitor 210 charges according to the voltage of the input signal VIN. After the first capacitor 210 is charged, the first and second switches 225, 230 are opened (OFF) to hold the charge of the first capacitor 210. In addition, the input terminal of the amplifier 200 provides a high impedance so that the charge is held in the first capacitor 210.

The integrator 110 may sum an output voltage from the second signal converter 125 and the voltage of the first capacitor 210 (i.e., a summed voltage).

During integration, the amplifier 200, the first capacitor 210, the second capacitor 205, and the resistor 220 operate together as an op-amp integrator circuit that generates an output voltage that is proportional to the integral of the summed voltage.

權利要求

1
微信群二維碼
意見反饋