Step 18. Clean off mask. O2 descum or ash all organics off wafer.
Step 19. Use photolithography to mask areas which will not have Plated Metal deposited.
Step 20. Plate areas with ?4-5 um of Metal (typically Au) or Cu if diffusion barrier can be deposited first.
Step 21. Use photolithography to mask areas which will not have Solder deposited.
Step 22. Deposit Solder Metal (Typically AuSn/Au eutectic composition of 80% Au/20% Sn by atomic weight. Total thickness of AuSn layer ?40000 A (4 microns) or more with ?500 A Au on top to stop any oxidation of Sn. This layer can be patterned and deposited on the submount with electrical waveguide which is bonded to the laser grid.
Embodiment 3 for US Pat App Pub 2017/0033535—Top-Emitting Oxidation
In a third embodiment, oxidation rather than ion implantation is used to create the grid of top-emitting lasing regions within the single structure. For example, a patterned etch can isolate conductive paths in a single structure, creating a grid of light sources. This structure exhibits multiple laser emission points from the single structure. The lasing structure is isolated with an etched region from the ground contact that forms the outside perimeter of the chip. This structure for Embodiment 3 is top emitting. The conductive areas of the grid are where light will be emitted. The positive electrical contact can be a grid with openings where the light is emitted.