In the example of FIG. 3, the Path 1 node can be coupled to an AC ground through a shunt circuit 141 having a plurality of FETs arranged in series. The gates, sources, and drains of such FETs can be biased as shown to allow the shunt circuit 141 to be turned ON when the corresponding series circuit 131 is OFF, and to be turned OFF when the series circuit 131 is ON. Such a shunt circuit can, for example, improve isolation between the Path 1 node and other nodes of the T/R switch 112.

Similarly, the second path (Path 2) can include a series circuit 132 having a plurality of FETs arranged in series. The gates, sources, and drains of such FETs can be biased as shown to allow the series circuit 132 to be turned ON for passing of an RF signal, and to be turned OFF to block passage of an RF signal. The Path 2 node can be the second of the two throws, and can be coupled to the PA (110 in FIG. 1).

In the example of FIG. 3, the Path 2 node can be coupled to an AC ground through a shunt circuit 142 having a plurality of FETs arranged in series. The gates, sources, and drains of such FETs can be biased as shown to allow the shunt circuit 142 to be turned ON when the corresponding series circuit 132 is OFF, and to be turned OFF when the series circuit 132 is ON. Such a shunt circuit can, for example, improve isolation between the Path 2 node and other nodes of the T/R switch 112.