The SPDT switch shown in FIG. 3 can be configured to support high linearity and low loss RF paths. For higher data rate and wider bandwidth operation, intermodulation can be an important design parameter. To linearize a given switch path, it is desirable to have the voltage waveforms across each FET in a stack be evenly distributed.
In the example of FIG. 3, two multi-gate MOS switch FETs are shown to be implemented to construct both series and shunt paths for each switch throw to minimize or reduce insertion loss and maximize or increase isolation at high frequency. When the parasitic capacitance of multiple stacked FETs in a shunt path is well designed and balanced, the RF voltage swing can be evenly distributed across each drain-source FET junction. In some embodiments, other important design criteria can include, for example, choice of FET width and number of FET stacks.
The maximum transmit power can be calculated or estimated by an equation
