log
10
?
(
[
n
?
(
Vgs
+
Vth
)
×
2
]
2
2
×
Z
o
)
2
(
1
)
where Z0 represents a characteristic impedance of the measurement system, Vgs represents a control voltage difference between the gate and source (or drain), Vth represents a threshold voltage of the switch FET, and n represents a number of cascaded switch FET.