A fifth aspect provides a terminal device, which includes a processor, a transceiver and a memory. The processor, the transceiver and the memory may communicate with one another through an internal connecting path. The memory is configured to store an instruction, and the processor is configured to execute the instruction stored in the memory. When the processor executes the instruction stored in the memory, such execution enables the terminal device to execute the method in the first aspect or any possible implementation mode of the first aspect, or such execution enables the terminal device to implement the terminal device provided in the third aspect.

A sixth aspect provides a network device, which includes a processor, a transceiver and a memory. The processor, the transceiver and the memory may communicate with one another through an internal connecting path. The memory is configured to store an instruction, and the processor is configured to execute the instruction stored in the memory. When the processor executes the instruction stored in the memory, such execution enables the network device to execute the method in the second aspect or any possible implementation mode of the second aspect, or such execution enables the network device to implement the network device provided in the fourth aspect.

A seventh aspect provides a system chip, which includes an input interface, an output interface, a processor and a memory. The processor is configured to execute an instruction stored in the memory. When the instruction is executed, the processor may implement the method in the first aspect or any possible implementation mode of the first aspect.