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Photoelectric conversion device and method of driving photoelectric conversion device

專利號
US11039057B2
公開日期
2021-06-15
申請人
CANON KABUSHIKI KAISHA（JP Tokyo）
發(fā)明人
Kei Ochiai
IPC分類
H04N5/232
技術(shù)領(lǐng)域
readout,pixel,row,pixels,signal,in,th,circuit,control,conversion
地域： Tokyo

摘要

A photoelectric conversion device includes a pixel region where pixels are arranged to form rows and columns, and a pixel control circuit that supplies control signals to the pixels. The pixel region includes first to fourth regions, a first pixel in the first region and a second pixel in the second region are arranged on different columns on a first row, a third pixel in the third region and a fourth pixel in the fourth region are arranged on different rows on a first column, and the first row on which the first and second pixels are arranged is arranged between rows on which the third and fourth pixels are arranged. The pixel control circuit simultaneously reads out pixel signals of the first and second pixels in a first period and simultaneously reads out pixel signals of the third and fourth pixels in a second period.

說明書

Note that, while the end time of the one exposure period and the start time of the subsequent exposure period are defined as the same time by the operation of controlling the transfer transistors M1 from an on-state to an off-state in the drive example described above, which can be separately defined by using the charge drain transistor M7. In the period of time T1 to time T5, for example, the charge drain transistor M7 is controlled to be temporarily turned on. Thereby, a timing of controlling the charge drain transistor M7 from an on-state to an off-state can be defined as the start time of the subsequent exposure period. By using the charge drain transistor M7, it is possible to improve flexibility in setting of the length of the exposure period.

FIG. 5 is a timing diagram illustrating a readout operation in the photoelectric conversion device of the present embodiment. FIG. 5 illustrates the control signal pSEL1 of the select transistor M5, the control signal pSEL2 of the select transistor M6, the control signal pRES of the reset transistor M3, and the control signal pTX2 of the transfer transistor M2 out of the control signals of the pixel P. When each of these control signals is at a high level, the corresponding transistor is in an on-state. Further, when each of these control signals is at a low level, the corresponding transistor is in an off-state. Here, the first direction refers is referred to as the horizontal direction, and the second direction is referred to as the vertical direction.

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