During the period from time T21 to time T22, the pixel control circuit 20 controls the control signal pSEL2 supplied to the control line 14 on the b-th column to the high level. Thereby, the select transistors M6 of the pixels P belonging to the b-th column are turned on, and the pixels P belonging to the b-th column are selected. That is, the pixels P belonging to the b-th column are ready for outputting pixel signals to the readout circuit 50 via the output lines 18 on the corresponding rows.
A period in which the control signal pRES is at the high level out of the period from time T21 to time T22 of
A noise signal and a light signal read out from the pixels P belonging to the b-th column to the readout circuit 50 are differentially processed in the CDS circuit provided in the readout circuit 50 to form image data on the b-th column.