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Photoelectric conversion device and method of driving photoelectric conversion device

專利號
US11039057B2
公開日期
2021-06-15
申請人
CANON KABUSHIKI KAISHA（JP Tokyo）
發(fā)明人
Kei Ochiai
IPC分類
H04N5/232
技術(shù)領(lǐng)域
readout,pixel,row,pixels,signal,in,th,circuit,control,conversion
地域： Tokyo

摘要

A photoelectric conversion device includes a pixel region where pixels are arranged to form rows and columns, and a pixel control circuit that supplies control signals to the pixels. The pixel region includes first to fourth regions, a first pixel in the first region and a second pixel in the second region are arranged on different columns on a first row, a third pixel in the third region and a fourth pixel in the fourth region are arranged on different rows on a first column, and the first row on which the first and second pixels are arranged is arranged between rows on which the third and fourth pixels are arranged. The pixel control circuit simultaneously reads out pixel signals of the first and second pixels in a first period and simultaneously reads out pixel signals of the third and fourth pixels in a second period.

說明書

A photoelectric conversion device and a method of driving the same according to a second embodiment of the present invention will be described with reference to FIG. 6. FIG. 6 is a block diagram illustrating a general configuration of the photoelectric conversion device according to the present embodiment. The same components as those in the photoelectric conversion device according to the first embodiment are labeled with the same reference, and the description thereof will be omitted.

In the present embodiment, a specific configuration example of the readout circuits 30 and 50 and the operation thereof will be described. Other configurations and respective operations are the same as those in the photoelectric conversion device according to the first embodiment.

As illustrated in FIG. 6, the readout circuit 30 of the photoelectric conversion device 100 according to the present embodiment includes a plurality of comparator circuits 32, a ramp signal generation circuit 36, a counter circuit 38, and a signal processing circuit 40.

The plurality of comparator circuits 32 are provided in association with respective columns of the pixel array in the pixel region 10. Each of the plurality of comparator circuits 32 is connected to the output line 16 on a corresponding column. Further, each of the plurality of comparator circuits 32 is connected to the ramp signal generation circuit 36, the counter circuit 38, and the signal processing circuit 40. Note that, in FIG. 6, depiction of the control circuit 70 is omitted.

權(quán)利要求

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