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Image sensor and electronic camera

專利號
US11039093B2
公開日期
2021-06-15
申請人
NIKON CORPORATION(JP Tokyo)
發(fā)明人
Atsushi Komai
IPC分類
H04N5/347; H04N5/374
技術(shù)領(lǐng)域
pixel,signal,pixels,vertical,unit,vl1,in,vl2,first,electric
地域: Tokyo

摘要

An image sensor, includes: a plurality of pixels arranged along a first direction, each of which includes a photoelectric conversion unit that generates an electric charge through photoelectric conversion of light, and outputs a signal generated based upon the electric charge generated in the photoelectric conversion unit; a first signal line to which signals from one or more pixels among the plurality of pixels are output; a second signal line to which a signal from another pixel among the plurality of pixels is output; and an arithmetic unit that executes an arithmetic operation with a signal generated by combining the signals from the one or more pixels output to the first signal line and the signal output to the second signal line.

說明書

The first electric current source 25 is connected to the individual pixels 10 via the first vertical signal line VL1, whereas the second electric current source 26 is connected to the individual pixels 10 via the second vertical signal line VL2. The first electric current source 25 and the second electric current source 26 each generate an electric current used to read out signals from each of the pixels 10. The first electric current source 25 provides an electric current having been generated therein to the first vertical signal line VL1 and to the first selection unit 16 and the amplifier unit 15 in each pixel 10. Likewise, the second electric current source 26 provides an electric current having been generated therein to the second vertical signal line VL2 and to the second selection unit 17 and the amplifier unit 15 in each pixel 10. It is to be noted that the electric current provided from the first electric current source 25 and the electric current provided from the second electric current source 26 assume values substantially equal to each other.

The arithmetic unit 50, which is configured so as to include an amplification unit 60, capacitors 51, 52 and 53 and switches SW1, SW2 and SW3, executes an arithmetic operation so as to add together a signal input to the capacitor 51 and a signal input to the capacitor 52. ON/OFF control of the switches SW1, SW2 and SW3, each constituted with a transistor, is executed by the vertical control unit 70.

權(quán)利要求

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