A pixel signal generated based upon an electric charge generated in the photoelectric conversion unit 11 of the pixel 10 (1, 1) in the first row is read out to the first vertical signal line VL1 via the first selection unit 16 of the pixel 10 (1, 1). Since the switches SW1 and SW3 are both in an ON state, the pixel signal from the pixel 10 (1, 1) having been output on the first vertical signal line VL1 is input to both the capacitor 51 and the capacitor 52. The arithmetic unit 50 outputs, via the output terminal 63, a signal obtained by adding together and averaging the pixel signal from the pixel 10 (1, 1) input to the capacitor 51 and the pixel signal from the pixel 10 (1, 1) input to the capacitor 52, as a pixel signal derived from the pixel 10 (1, 1).
After reading out the pixel signal from the pixel 10 in the first row, the vertical control unit 70 sets the first selection unit 16 in an ON state and sets the second selection unit 17 in an OFF state at the pixel 10 (2, 1) in the second row. In addition, the vertical control unit 70 sets the first selection units 16 and the second selection units 17 in the pixels 10 in rows other than the second row in an OFF state. A pixel signal from the pixel 10 (2, 1) is read out to the first vertical signal line VL1 via the first selection unit 16 of the pixel 10 (2, 1). The arithmetic unit 50 outputs, via the output terminal 63, a signal obtained by adding together and averaging the pixel signal from the pixel 10 (2, 1) input to the capacitor 51 and the pixel signal from the pixel 10 (2, 1) input to the capacitor 52.